Parallelism
The following sequence implements an atomic exchange on the memory location specified by the contents of $s1:
again: addi $t0, $zero, 1 #copy locked value
ll $t1, 0($s1) #load linked
sc $t0, 0($s1) #store conditional
beq $t0, $zero, again #branch if store fails
add $s4, $zero, $t1 #put load value in $s4
Any time a processor intervenes and modifies the value in memory between the ll and sc instructions, the sc returns 0 in $t0, causing the code sequence to try again. At the end of this sequence the contents of $s4 and the memory location specified by $s1 have been atomically exchanged.
Pseudoinstructions
As
move $t0, $t1
is actually
add $t0, $zero, $t1
.
Others like: blt, bgt, bge, ble and etc. The cost is reserving one register, $at, for use by the assembler.
