1 特性

1.1 通用特性

• 電源范圍：2.4V ~ 3.6V
• 最高IO口電壓：5V
• ADC/DAC精度：24bit
• 控制總線：L3/I2C, 都有兩個地址可選
  
• ADC采樣率范圍：8~55kHz
• DAC采樣率范圍：8~100kHz
• 電源管理單元
  • 獨立電源管理ADC/AVC/DAC/PLL/耳機(jī)驅(qū)動
  • ADC/PGA等模電模組可以獨立關(guān)閉其電源
  • 當(dāng)DAC/ADC電源關(guān)閉時，它們使用的時鐘也會一起關(guān)閉來節(jié)省電源
  • 默認(rèn)情況下纯蛾，IC上電后巡雨，整個芯片都處于電源關(guān)閉狀態(tài)
• ADC和DAC可以運行在不同的時鐘頻率下，不然選擇系統(tǒng)時鐘(SYSCLK)暮现，不然選擇WSPLL
• ADC和PGA都集成了高通濾波器來去除直流偏置
• 抽取濾波器配備了數(shù)字自動增益控制模塊
• 單聲道麥克風(fēng)輸入配備了29dB固定增益的低噪聲放大器(LNA)和0~30dB可變增益控制(2dB步進(jìn))
• DAC集成了數(shù)字濾波器
• 有單獨的單端線路輸出和立體聲耳機(jī)輸出还绘，均可驅(qū)動16Ω的負(fù)載。耳機(jī)輸出內(nèi)置了短路保護(hù)栖袋，并且可以通過L3/I2C來讀取短路狀態(tài)
• 插值器中集成了數(shù)字靜音檢測拍顷，可通過L3/I2C來從讀取播放時的靜音狀態(tài)

1.2 多格式輸入

• 從機(jī)BCK、WS信號輸入
• I2S總線格式
• MSB對齊格式兼容
• LSB對齊格式兼容

1.3 多格式輸出

• 數(shù)字輸出可選：
  • 抽取器ADC信號輸出
  • 插值器DSP中的數(shù)字混音器輸出

1.4 ADC前置特性

• ADC配合抽取器可以使用系統(tǒng)時鐘(SYSCLK)塘幅，也可以使用從WSI生成的WSPLL時鐘
• 立體聲線路輸入可配備PGA來獲取0 ~ 24dB的增益(3dB步進(jìn))
• 麥克風(fēng)單聲道輸入可配備LNA/VGA來獲取29dB的固定增益0 ~ 30dB可變增益控制
• 左右聲道可獨立控制音量和靜音昔案，控制范圍從+24dB ~ -63.5dB，0.5dB步進(jìn)

1.5 DAC特性

• DAC配合插值器可以使用系統(tǒng)時鐘(SYSCLK)电媳，也可以使用從WSI生成的WSPLL時鐘
• 左右聲道可通過L3/I2C進(jìn)行獨立的對數(shù)音量控制踏揣，控制范圍從+0dB ~ -78dB，0.25dB步進(jìn)
• 數(shù)字化頻段調(diào)整匾乓，重低音捞稿、高音可通過L3/I2C調(diào)節(jié)
• 數(shù)字化去加重采樣頻率支持：32, 44.1, 48, 96kHz
• cos曲線包絡(luò)靜音
• 輸出信號極性可控
• 相同采樣率下，ADC可和I2S輸入信號一起混音輸出

2 功能描述

2.1 時鐘模式

UDA1380支持使用I2S總線上主機(jī)提供的SYSCLK(或叫MCLK)拼缝，也支持由WS分頻產(chǎn)生的內(nèi)部時鐘作為MCLK(WSPLL模式)娱局。

• 使用SYSCLK時，可以用跳線指定SYSCLK使用TX_MCLK還是RX_MCLK咧七，同時也需要指定輸入的SYSCLK時鐘頻率是采樣頻率的256倍衰齐、384倍、512倍還是768倍(詳見I2S協(xié)議對MCLK的定義)
• 使用WSPLL時继阻，只能使用WSI信號作為內(nèi)部時鐘的分頻源娇斩，同時需要指定WSI信號的頻率范圍是在6.25 ~ 12.5kHz仁卷、
  12.5 ~ 25kHz、25 ~ 50kHz還是50 ~ 100kHz犬第。

UDA1380有幾種時鐘模式可以使用:

• ADC和DAC都同時運行在SYSCLK下锦积，此時WSPLL就應(yīng)該處于斷電模式
• ADC和DAC都同時運行在WSPLL下，那么需要WSI輸入的信號來分頻產(chǎn)生內(nèi)部時鐘
• ADC可使用SYSCLK信號歉嗓，而DAC可使用與SYSCLK頻率不同的WSI產(chǎn)生的內(nèi)部時鐘信號

如果只使用UDA1380的模擬ADC輸入功能和I2S數(shù)字信號輸出丰介，而沒有I2S數(shù)字信號輸入，則沒有WSI信號可用鉴分，是否會有問題哮幢？(待朕后續(xù)求證~=￣ω￣=)

2.1.1 WSPLL使用

2.1.2 時鐘分布

2.2 ADC前置模擬信號

2.2.1 應(yīng)用模式和斷電模式

2.3 ADC抽取濾波器

2.3.1 負(fù)載檢測

2.3.2 音量控制

2.3.3 靜音

2.3.4 自動增益控制

2.4 DAC插值濾波器

2.4.1 數(shù)字靜音

2.4.2 聲音特性

2.5 噪聲整形器

2.6 濾波流數(shù)模轉(zhuǎn)換器(FSDAC)

2.6.1 介紹

2.6.2 模擬混音器輸入

2.7 耳機(jī)驅(qū)動

2.8 混音器

2.8.1 數(shù)字混音器

2.8.2 模擬混音器

2.9 應(yīng)用模式

2.10 帶電重置

2.11 斷電模式

2.11.1 模擬前置輸入

2.11.2 FSDAC電源控制

2.12 啪嗒聲的抑制

2.13 數(shù)字音頻數(shù)據(jù)輸入輸出

2.13.1 數(shù)字音頻輸入接口

2.13.2 數(shù)字音頻輸出接口

2.14 數(shù)字音頻輸入接口

3 I2C接口描述

UDA1380即能支持I2C接口也能L3接口，I2C和L3接口都是通過相同的寄存器來控制模塊的特性志珍。
單片機(jī)和UDA1380之間的數(shù)據(jù)交換和控制信息都通過下面幾個針腳來完成：

• SCL橙垢，I2C時鐘腳
• SDA，I2C數(shù)據(jù)腳

3.1 尋址

UDA1380的I2C地址為0X30(A1位為0)或0x34(A1位為1)伦糯。和大多數(shù)I2C設(shè)備一樣柜某，寫數(shù)據(jù)時，需要對地址+1敛纲，即：

• 讀數(shù)據(jù)時喂击，地址為0x30或0x34
• 寫數(shù)據(jù)時，地址為0x31或0x35

3.2 寄存器

3.2.1 [0x00] 評估模式童叠、WSPLL配置框喳、時鐘分頻配置、時鐘選擇配置

#define TRUE          1
#define FALSE         0
#define SYSCLK        0
#define WSPLL         1
#define SYS_DIV_256FS 0
#define SYS_DIV_384FS 1
#define SYS_DIV_512FS 2
#define SYS_DIV_768FS 3
#define PLL_6.25_12.5 0
#define PLL_12.5_25   1
#define PLL_25_50     2
#define PLL_50_100    3

struct {
    uint8 evaluationMode           : 3; // [15:13], default = 0
    uint8 reserved0                : 1; // [12],    default = 0
    uint8 adcClockEnabled          : 1; // [11],    default = TRUE
    uint8 decimatorClockEnabled    : 1; // [10],    default = FALSE
    uint8 fsdacClockEnabled        : 1; // [9],     default = TRUE
    uint8 interpolatorClockEnabled : 1; // [8],     default = TRUE
    uint8 reserved1                : 2; // [7:6],   default = 0
    uint8 adcClockSelect           : 1; // [5],     default = SYSCLK
    uint8 dacClockSelect           : 1; // [4],     default = SYSCLK
    uint8 systemClockInputDividers : 2; // [3:2],   default = SYS_DIV_256FS, input clock on pin SYSCLK
    uint8 pllSetting               : 2; // [1:0],   default = PLL_25_50,     input frequency range(kHz) on pin WSI
};

• ADC為模擬輸入的轉(zhuǎn)為數(shù)字信號的轉(zhuǎn)換器厦坛，在UDA1380中信號是以數(shù)字信號形式來處理的五垮，所以要輸入模擬音頻信號時(Line in或Mic)都需要啟用ADC
• Decimator這里準(zhǔn)確的說應(yīng)該是抽取濾波器，因為數(shù)字信號在ADC里是以不斷采樣模擬信號得來的杜秸，所以采樣后會對信號做一定的濾波來優(yōu)化信號的質(zhì)量放仗。所以啟用ADC時，伴隨就要啟用DecimatorFilter了
• FSDAC為UDA1380使用的DAC撬碟，全稱為流濾波數(shù)模轉(zhuǎn)換器(Filter Stream DAC)诞挨。它從噪聲整形器接受字節(jié)流來轉(zhuǎn)換為模擬音頻信號輸出
• Interpolator這里指的是插值濾波器莉撇，離散的數(shù)字信號轉(zhuǎn)換為連續(xù)的模擬音頻信號時，會通過插值濾波器的處理惶傻，提高輸出的模擬信號的質(zhì)量棍郎。所以啟用DAC來輸出模擬信號時，伴隨需要啟用InterpolatorFilter來優(yōu)化數(shù)模轉(zhuǎn)換
• ADC和DAC可以選擇SYSCLK和WSPLL兩種時鐘银室，但因為SYSCLK需要的MCLK是高頻時鐘涂佃，對布線要求高，容易產(chǎn)生干擾蜈敢，所以很多方案都放棄了MCLK辜荠。所以建議采用WSPLL來通過WS信號生成內(nèi)部所需的時鐘

3.2.2 [0x01] I2S總線IO配置

#define INPUT_I2S           0
#define INPUT_LSB_16BITS    1
#define INPUT_LSB_18BITS    2
#define INPUT_LSB_20BITS    3
#define INPUT_MSB           4
#define OUTPUT_I2S          0
#define OUTPUT_LSB_16BITS   0
#define OUTPUT_LSB_18BIS    0
#define OUTPUT_LSB_20BITS   0
#define OUTPUT_LSB_24BITS   0
#define OUTPUT_MSB          0
#define DECIMATOR           0
#define DIGITAL_MIXER       1
#define SLAVE               0
#define MASTER              1

struct {
    uint8 reserved0                    : 5; // [15:11], default = 0
    uint8 digitalDataInputFormat       : 2; // [10:8],  default = INPUT_I2S
    uint8 reserved1                    : 1; // [7],     default = 0
    uint8 digitalOutputInterfaceSource : 1; // [6],     default = DECIMATOR
    uint8 reserved2                    : 1; // [5],     default = 0 
    uint8 digitalOutputInterfaceMode   : 1; // [4],     default = SLAVE
    uint8 reserved3                    : 1; // [3],     default = 0 
    uint8 digitalDataOutputFormat      : 3; // [2:0],   default = OUTPUT_I2S
};

3.2.3 [0x02] 電源控制

#define TRUE      1
#define FALSE     0
#define POWER_OFF 0
#define POWER_ON  1

struct {
    uint8 pllPower       : 1; // [15],    default = POWER_OFF
    uint8 reserved0      : 1; // [14],    default = 0
    uint8 headphonePower : 1; // [13],    default = POWER_OFF
    uint8 reserved1      : 2; // [12:11], default = 0
    uint8 dacPower       : 1; // [10],    default = POWER_OFF
    uint8 reserved2      : 1; // [9],     default = 0
    uint8 biasPower      : 1; // [8],     default = POWER_OFF
    uint8 avcEnabled     : 1; // [7],     default = FALSE,     enable the analog mixer
    uint8 avcPower       : 1; // [6],     default = POWER_OFF
    uint8 reserved3      : 1; // [5],     default = 0
    uint8 lnaPower       : 1; // [4],     default = POWER_OFF
    uint8 pgaLeftPower   : 1; // [3],     default = POWER_OFF, left channel PGA power
    uint8 adcLeftPower   : 1; // [2],     default = POWER_OFF, left channel ADC power
    uint8 pgarRightPower : 1; // [1],     default = POWER_OFF, right channel PGA power
    uint8 adcRightPower  : 1; // [0],     default = POWER_OFF, right channel PGA power
};

3.2.4 [0x03] 模擬混音器

#define AVC_MUTE        0x3F
#define AVC_MAX_VOLUME  0
#define AVC_MIN_VOLUME  44

struct {
    uint8 reserved0         : 2; // [15:14], default = 0
    uint8 analogVolumeLeft  : 6; // [13:8],  default = AVC_MUTE, range is [0, 44] mapping to [16.5dB, -∞dB], step is 0.5dB
    uint8 reserved1         : 2; // [7:6],   default = 0
    uint8 analogVolumeRight : 6; // [5:0],   default = AVC_MUTE, range is [0, 44] mapping to [16.5dB, -∞dB], step is 0.5dB
};

3.2.5 [0x04] 預(yù)留

#define RESREVED 0x2

struct {
    uint8 reserved0 : 5; // [15:11], default = 0
    uint8 RSV0      : 3; // [10:8],  default = RESREVED
    uint8 reserved1 : 5; // [7:3],   default = 0
    uint8 RSV1      : 3; // [2:0],   default = RESREVED
};

3.2.6 [0x10] 主音量控制

#define MASTER_MUTE       0xFC
#define MASTER_MAX_VOLUME 0
#define MASTER_MIN_VOLUME 252

struct {
    uint8 masterVolumeRight : 8; // [15:8], default = MASTER_MAX_VOLUME, range is [0, 252] mapping to [0dB, -78dB], step is 0.25dB
    uint8 masterVolumeLeft  : 8; // [7:0],  default = MASTER_MAX_VOLUME, range is [0, 252] mapping to [0dB, -78dB], step is 0.25dB
};

3.2.7 [0x11] 混音器音量控制

#define MIXER_MUTE       0xFC
#define MIXER_MAX_VOLUME 0
#define MIXER_MIN_VOLUME 228

struct {
    uint8 digitalMixerVolume2 : 8; // [15:8], default = MIXER_MAX_VOLUME, range is [0, 228] mapping to [0dB, -72dB], step is 0.25dB
    uint8 digitalMixerVolume1 : 8; // [7:0],  default = MIXER_MUTE,       range is [0, 228] mapping to [0dB, -72dB], step is 0.25dB
};

3.2.8 [0x12] 模式選擇、左右聲道重低音調(diào)節(jié)抓狭、左右聲道高音調(diào)節(jié)

#define TONE_LEVEL_FLAT      0
#define TONE_LEVEL_MIN       1
#define TONE_LEVEL_MID       2
#define TONE_LEVEL_MAX       3
#define TONE_TREBLE_MIN      0
#define TONE_TREBLE_MAX      3
#define TONE_BASS_BOOST_MIN  0
#define TONE_BASS_BOOST_MAX  15

struct {
    uint8 toneLevel      : 2; // [15:14], default = TONE_LEVEL_FLAT 
    uint8 trebleLeft     : 2; // [13:12], default = TONE_TREBLE_MIN
    uint8 bassBoostLeft  : 4; // [11:8],  default = TONE_BBE_MIN
    uint8 reserved       : 2; // [7:6],   default = 0
    uint8 trebleRight    : 2; // [5:4],   default = TONE_TREBLE_MIN
    uint8 bassBoostRight : 4; // [3:0],   default = TONE_BBE_MIN
};

3.2.9 [0x13] 主靜音伯病、左右聲道去加重、左右聲道靜音

#define SOFTWARE_UNMUTE    0
#define SOFTWARE_MUTE      1
#define DEEMPHASIS_OFF     0
#define DEEMPHASIS_32KHZ   1
#define DEEMPHASIS_44.1KHZ 2
#define DEEMPHASIS_48KHZ   3
#define DEEMPHASIS_96KHZ   4

struct {
    uint8 reserved0          : 1; // [15],    default = 0
    uint8 masterMute         : 1; // [14],    default = SOFTWARE_MUTE
    uint8 reserved1          : 2; // [13:12], default = 0
    uint8 channel2Mute       : 1; // [11],    default = SOFTWARE_MUTE
    uint8 channel2Deemphasis : 3; // [10:8],  default = 0
    uint8 reserved2          : 3; // [7:4],   default = 0
    uint8 channel1Mute       : 1; // [3],     default = SOFTWARE_UNMUTE
    uint8 channel1Deemphasis : 3; // [2:0],   default = 0
};

3.2.10 [0x14] 混音器否过、靜音探測午笛、插值濾波器超采樣配置

#define DAC_OUTPUT_NORMAL            0
#define DAC_OUTPUT_INVERT            1
#define ORDER_3RD_SHAPER             0
#define ORDER_5RD_SHAPER             1
#define MIXING_OFF                   0
#define MIXING_CHANNEL1_SOLO         1
#define MIXING_BEFORE_PROCESS        2
#define MIXING_AFTER_PROCESS         3
#define NO_OVERRULING                0
#define OVERRULING                   1
#define SILENCE_DETECT_DISABLE       0
#define SILENCE_DETECT_ENABLE        1
#define SILENCE_DETECT_3200_SAMPLES  0
#define SILENCE_DETECT_4800_SAMPLES  1
#define SILENCE_DETECT_9600_SAMPLES  2
#define SILENCE_DETECT_19200_SAMPLES 3
#define OVERSAMPLING_1X              0
#define OVERSAMPLING_2X              1
#define OVERSAMPLING_4X              2

struct {
    uint8 dacPolarity            : 1; // [15],    default = DAC_OUTPUT_NORMAL
    uint8 noiseShaperOrder       : 1; // [14],    default = ORDER_3RD_SHAPER
    uint8 mixerSignalControl     : 2; // [13:12], default = MIXING_OFF
    uint8 reserved0              : 4; // [11:8],  default = 0
    uint8 silenceDetector        : 1; // [7],     default = NO_OVERRULING
    uint8 silenceDetectorEnabled : 1; // [6],     default = SILENCE_DETECT_DISABLE
    uint8 silenceDetectorSetting : 2; // [5:4],   default = SILENCE_DETECT_3200_SAMPLES
    uint8 reserved1              : 2; // [3:2],   default = 0
    uint8 oversampling           : 2; // [1:0],   default = OVERSAMPLING_1X
};

3.2.11 [0x18] 插值濾波器狀態(tài)

3.2.12 [0x20] 抽取器音量控制

#define ADC_GAIN_MAX  48
#define ADC_GAIN_NONE 0
#define ADC_GAIN_MIN  -127

struct {
    int8 adcVolumeLeft  : 8; // [15:8], default = ADC_GAIN_NONE, range is [-127, 48] mapping to [-∞dB, 24dB], step is 0.5dB
    int8 adcVolumeRight : 8; // [7:0],  default = ADC_GAIN_NONE, range is [-127, 48] mapping to [-∞dB, 24dB], step is 0.5dB
};

3.2.13 [0x21] 可編程增益放大器配置和靜音

#define DECIMATOR_UNMUTE             0
#define DECIMATOR_MUTE               1
#define ADC_INPUT_AMPLIFIER_GAIN_MIN 0
#define ADC_INPUT_AMPLIFIER_GAIN_MAX 8

struct {
    uint8 decimatorMute              : 1; // [15],    default = DECIMATOR_MUTE
    uint8 reserved0                  : 3; // [14:12], default = 0
    uint8 adcInputAmplifierGainRight : 4; // [11:8],  default = ADC_INPUT_AMPLIFIER_GAIN_MIN, range is [0, 8] mapping to [0dB, 24dB], step is 3dB
    uint8 reserved1                  : 3; // [7:4],   default = 0
    uint8 adcInputAmplifierGainLeft  : 4; // [3:0],   default = ADC_INPUT_AMPLIFIER_GAIN_MIN, range is [0, 8] mapping to [0dB, 24dB], step is 3dB
};

3.2.14 [0x22] ADC配置

#define ADC_OUTPUT_NORMAL            0
#define ADC_OUTPUT_INVERT            1
#define ADC_INPUT_LINEIN             0
#define ADC_INPUT_LNA                1
#define MIC_INPUT_RIGHT_ADC          0
#define MIC_INPUT_LEFT_ADC           1
#define DC_FILTER_ENABLE             0
#define DC_FILTER_BYPASS             1
#define DC_FILTER_OFF                0
#define DC_FILTER_ON                 1

struct {
    uint8 reserved0       : 3; // [15:13], default = 0
    uint8 adcPolarity     : 1; // [12],    default = ADC_OUTPUT_NORMAL
    uint8 micInputVGAGain : 4; // [11:8],  default = MIC_INPUT_GAIN_MIN, range is [0, 15] mapping to [0dB, 30dB], step is 2dB
    uint8 reserved1       : 4; // [7:4],   default = 0
    uint8 leftADCFunction : 1; // [3],     default = ADC_INPUT_LINEIN
    uint8 micInputChannel : 1; // [2],     default = MIC_INPUT_RIGHT_ADC
    uint8 dcFilterBypass  : 1; // [1],     default = DC_FILTER_BYPASS
    uint8 dcFileterPower  : 1; // [0],     default = DC_FILTER_OFF
};

3.2.15 [0x23] 自動增益控制

#define AGC_TIME_0         0 // 44.1kHz(attack:11ms, decay:100ms) 8kHz(attack:61ms,   decay:551ms)
#define AGC_TIME_1         1 // 44.1kHz(attack:16ms, decay:100ms) 8kHz(attack:88.2ms, decay:551ms)
#define AGC_TIME_2         2 // 44.1kHz(attack:11ms, decay:200ms) 8kHz(attack:61ms,   decay:1102ms)
#define AGC_TIME_3         3 // 44.1kHz(attack:16ms, decay:200ms) 8kHz(attack:88.2ms, decay:1102ms)
#define AGC_TIME_4         4 // 44.1kHz(attack:21ms, decay:200ms) 8kHz(attack:116ms,  decay:1102ms)
#define AGC_TIME_5         5 // 44.1kHz(attack:11ms, decay:400ms) 8kHz(attack:61ms,   decay:2205ms)
#define AGC_TIME_6         6 // 44.1kHz(attack:16ms, decay:400ms) 8kHz(attack:88.2ms, decay:2205ms)
#define AGC_TIME_7         7 // 44.1kHz(attack:21ms, decay:400ms) 8kHz(attack:116ms,  decay:2205ms)
#define AGC_LEVEL_NEG_5.5  0 // -5.5dBFS
#define AGC_LEVEL_NEG_8    1 // -8dBFS
#define AGC_LEVEL_NEG_11.5 2 // -11.5dBFS
#define AGC_LEVEL_NEG_14   3 // -14dBFS
#define AGC_OFF            0
#define AGC_ON             1

struct {
    uint8 reserved0  : 5; // [15:11], default = 0
    uint8 agcTime    : 3; // [10:8],  default = AGC_TIME_0, 44.1kHz(attack:11ms, decay:100ms) 8kHz(attack:61ms,   decay:551ms)
    uint8 reserved1  : 4; // [7:4],   default = 0
    uint8 agcLevel   : 2; // [3:2],   default = AGC_LEVEL_NEG_5.5
    uint8 reserved2  : 1; // [1],     default = 0
    uint8 agcPower   : 1; // [0],     default = AGC_OFF
};

3.2.16 [0x28] 抽取器狀態(tài)

3.2.17 [0x7F] 恢復(fù)L3默認(rèn)值

此命令為軟件重置，不需要發(fā)送數(shù)據(jù)

名詞解釋

• ADC - Analog to Digit Converter, 模數(shù)轉(zhuǎn)換器
• DAC - Digit to Analog Converter, 數(shù)模轉(zhuǎn)換器
• AVC - Automatic Volumn Control, 自動音量控制
• PLL - Phase Locked Loop, 鎖相環(huán)
• PGA - Programmable Gain Amplifier, 可編程增益放大器
• LNA - Low Noise Amplifer, 低噪聲放大器
• FSDAC - Filter-Stream Digital-to-Analog Converter, 濾波流數(shù)模轉(zhuǎn)換器

草稿

/**
 * 1. 輸入: 啟用ADC line in
 *          禁用ADC Mic
 *          啟用I2S in
 * 2. 輸出：啟用DAC
 *          啟用Headphone driver
 *          禁用I2S out
 * 3. 時鐘：啟用WSPLL
 *
 * Line in: ADC + PGA
 *
 * REG_CLOCK = {
 *     EV:         000
 *     EN_ADC:     1
 *     EN_DEC:     1 // Decimator從ADC中把模擬信號抽取為數(shù)字信號叠纹，ADC要配合DEC使用
 *     EN_DAC:     1 // FSDAC
 *     EN_INT:     1 // Interpolater
 *     ADC_CLK:    1 // 1 for WSPLL, 0 for SYSCLK
 *     DAC_CLK:    1 // 1 for WSPLL, 0 for SYSCLK
 *     SYS_DIV:    0 // 0 for 256fs, 1 for 384fs, 2 for 512fs, 3 for 768fs
 *     PLL:        2 // 0 for 6.25~12.5kHz, 1 for 12.5~25kHz, 2 for 25~50kHz, 3 for 50~100kHz
 * }
 *
 * REG_I2S = {
 *     SFORI:      0 // 0 for I2S, 1 for LSB-16bits, 2 for LSB-18bits, 3 for LSB-20bits, 4 for MSB
 *     SEL_SOURCE: 1 // 0 for decimator as output, 1 for digital mixer output as output
 *     SIM:        0 // 0 for digital output interface as SLAVE, 1 for digital output interface as MASTER
 *     SFORO:      0 // 0 for I2S, 1 for LSB-16bits, 2 for LSB-18bits, 3 for LSB-20bits, 4 for LSB-24bits, 5 for MSB
 * }
 *
 * REG_PWR = {
 *     PON_PLL:    1 // 0 for WSPLL off, 1 for WSPLL on
 *     PON_HP:     1 // 0 for Headphone off, 1 for Headphone on
 *     PON_DAC:    1 // 0 for DAC off, 1 for DAC on
 *     PON_BIAS:   1 // 0 for ADC/AVC/FSDAC bias circuits off, 1 for ADC/AVC/FSDAC bias circuits on
 *     EN_AVC:     0 // 0 for mix in line put through digital mixer to ouput, 1 for enable mixing-in ADC line input(via AVC unit) to the line output directly
 *     PON_AVC:    0 // 0 for analog mixer off, 1 for analog mixer on
 *     PON_LNA:    0 // 0 for LNA/SDC off, 1 for LNA/SDC on
 *     PON_PGAL:   1 // 0 for PGA left off, 1 for PGA left on
 *     PON_PGAR:   1 // 0 for PGA right off, 1 for PGA right on
 *     PON_ADCL:   1 // 0 for ADC left off, 1 for ADC left on
 *     PON_ADCR:   1 // 0 for ADC right off, 1 for ADC right on
 *
 *     PON_HP and PON_DAC should be power on later for PLOP prevention
 * }
 *
 * REG_AMIX = { // The analog mixer has been power-off
 *     AVCL: 0x3F // 0 for max, 2b for min, 3f for mute
 *     AVCR: 0x3F // 0 for max, 2b for min, 3f for mute
 * }
 *
 * REG_MASTER_VOL = {
 *     MVCR: 0x20 // 0 for max, f8 for min, fc for mute
 *     MVCL: 0x20 // 0 for max, f8 for min, fc for mute
 * }
 *
 * REG_MIXER_VOL = {
 *     MVC_ANALOG:  0x00 // 0 for max, e0 for min, fc for mute, channel 2 is decomator
 *     MVC_DIGITAL: 0x00 // 0 for max, e0 for min, fc for mute, channel 1 is digital input
 * }
 *
 * REG_EQ = {}
 *
 * REG_MUTE = {
 *     MT_MASTER:  1 // 0 for unmute, 1 for mute
 *     MT_DIGITAL: 1 // 0 for unmute, 1 for mute
 *     DE_DIGITAL: 0 // 0 for off, 1 for 32kHz de-emphasis, 2 for 44.1kHz de-emphasis, 3 for 48kHz de-emphasis, 4 for 96kHz de-emphasis, disable it cause we have no emphasis process
 *     MT_ANALOG:  1 // 0 for unmute, 1 for mute
 *     DE_ANALOG:  0 // 0 for off, 1 for 32kHz de-emphasis, 2 for 44.1kHz de-emphasis, 3 for 48kHz de-emphasis, 4 for 96kHz de-emphasis, disable it cause we have no emphasis process
 *
 *     Unmute after starting
 * }
 *
 * REG_MIXER = {
 *     DAC_POL_INV: 0 // 0 for disable, 1 for enable
 *     SEL_NS:      1 // 0 for 3rd-order noise shaper(preferred at 8~32kHz), 1 for 5th-order noise shaper(preferred at 32~100kHz)
 *     MIX_POS:     0 // if MIX is 0 + MIX_POS is 0, mixing will be disabled
 *     MIX:         1 // 0 for disable mixer, 1 for enable mixer
 *
 *     MIX = 1, MIX_POS = 0, mixing will be executed before EQ processing
 * }
 */