建立功能模塊
// Author : liq
// File : tst_a4_and_b4.v
// Create : 2019-07-21 20:27:11
// Revise : 2019-07-21 20:27:11
// Editor : sublime text3, tab size (4)
// -----------------------------------------------------------------------------
module test_a4_and_b4(
input wire clk,
input wire[7:0] a,
input wire[7:0] b,
output reg[7:0] c);
always@(posedge clk)begin
c<=a&b;
end
endmodule
建立測試激勵模塊
// Author : liq
// File : tb_test_a4_and_b4.v
// Create : 2019-07-21 20:00:11
// Revise : 2019-07-21 20:00:11
// Editor : sublime text3, tab size (4)
// -----------------------------------------------------------------------------
`timescale 1ns/1ns
module tb_test_a4_and_b4();
reg clk1;
reg [7:0] a1;
reg [7:0] b1;
wire [7:0] c1;
initial begin
clk1=0;
a1=0;
b1=0;
end
always #10 clk1=~clk1;
always #10 a1={$random}%256;
always #10 b1={$random}%256;
test_a4_and_b4 test_a4_and_b4_inst(
.clk(clk1),
.a(a1),
.b(b1),
.c(c1)
);
endmodule
仿真結(jié)果
圖片1.png
