VHDL實現(xiàn)如下:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTIDY Trans38 IS
PORT(
? A:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
? Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
? );
END Trans38;
ARCHITECTURE behav OF trans38 IS
BEGIN
WITH A SELECT
Y<= ?"00000000"?SLL CONV_INTEGER(A)?when "0001",
? ? ? ? ? "00000000" SLL CONV_INTEGER(A) when "001" , ? ?--有效輸出為高電平
? ? ? ? ? "00000000" SLL CONV_INTEGER(A) when "010" ,
? ? ? ? ? "00000000" SLL CONV_INTEGER(A) when "011" ,
? ? ? ? ? "00000000" SLL CONV_INTEGER(A) when "100" ,
? ? ? ? ? "00000000" SLL CONV_INTEGER(A) when "101" ,
? ? ? ? ? "00000000" SLL CONV_INTEGER(A) when "110" ,
? ? ? ? ? "00000000" SLL CONV_INTEGER(A) when "111" ;
END behav;
注：來自互聯(lián)網(wǎng)复濒，未經(jīng)實機測試仁热，謹慎使用；
