分析題意
1.clk周期為10ns;
2.在測試樣例中,ia=0,延時10ns杂曲;ib=1,延時30ns灵妨;
3.oc=ia|ib解阅,時鐘上升沿跳變(本題理解為下降沿跳變)
功能模塊代碼
module tri_assigenments(
input clk,
input wire ia,
input wire ib,
output reg oc
);
always@(negedge clk)begin
oc=ia|ib;
end
endmodule
測試樣例代碼
module tb_tri_assigenments();
reg clk;
reg ia1;
reg ib1;
wire oc1;
initial begin
clk=0;
ia1=0;
ib1=1;
end
always #5 clk=~clk;
always #10 ia1={$random};
always #30 ib1={$random};
tri_assigenments tri_assigenments_inst(
.clk(clk),
.ia(ia1),
.ib(ib1),
.oc(oc1)
);
endmodule