1.component（元件）：元件可放在library內(nèi)，供所有使用者多次調(diào)用境钟。
元件聲明：
component label is
port( port_name: signal_mode signal_type;...);
end component;
元件實例化：
label：component_name port map(port_list);
2.幾種常見庫：
use ieee.std_logic_unsigned.all 使得std_logic_vector類型的數(shù)據(jù)像unsigned類型一樣操作锦担。
use ieee.std_logic_arith.all 包括有符號數(shù)和無符號數(shù)的算術(shù)運算和比較運算。
3.信號與變量：
常量（默認值）：constant const_name: type := value;
可在包慨削、實體或結(jié)構(gòu)體中聲明洞渔。
信號（實際連線）：signal name：type [range] [:= initial_value];
表示端口或內(nèi)部連接。不能簡單理解為某端口的電壓缚态，0磁椒、1、Z玫芦，一個信號對應(yīng)一部分的觸發(fā)和相應(yīng)的動作衷快。比如temp<=temp+1對應(yīng)某個寄存器中數(shù)值加一。
變量（局部）：variable name：type [range] [:= initial_value];
特點：立即賦值姨俩。綜合時會生成額外的寄存器蘸拔。
4. others => '0' 用于對數(shù)組中的各個元素賦值‘0’；others => NULL 用于某些語句（例如case語句）中的子句（例如when子句）不做任何賦值环葵。
5.Example: Legal and illegal operations with std_logic_vector.
LIBRARY ieee;
USE ieee.std_logic_1164.all;? ? -- no extra package required
...
SIGNAL a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
...
v <= a + b;? ? ? -- illegal (arithmetic operation not OK)
w <= a AND b;? ? -- legal (logical operation OK)
Despite the constraint mentioned above, there is a simple way of allowing data of
type STD_LOGIC_VECTOR to participate directly in arithmetic operations. For
that, theieeelibrary provides two packages,std_logic_signedandstd_logic_unsigned,
which allow operations with STD_LOGIC_VECTOR data to be performed as if the
data were of type SIGNED or UNSIGNED, respectively.
6.Description
The following error occurs in NGDBuild:
"Error: 432 - Logical block 'xxxx' with type 'xxx' is unexpanded."
Solution
NGDBuild issues this error when it cannot resolve all of the components/modules for the entire design.
For example, suppose you have an HDL design that instantiates black-box modules, and the module description for these black-boxes is contained in an EDIF file. If the EDIF file is not in the macro search path or the project directory, NGDBuild issues this error.
To avoid this problem, verify that the module description file has the correct name and is located in the macro search path or project directory.
