RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The final user-level ISA specification, a draft compressed ISA specification, a draft privileged ISA specification, and a suite of RISC-V software tools including a GNU/GCC software tool chain, GNU/GDB debugger, an LLVM compiler, a Spike ISA simulator, QEMU, and a verification suite is available for download now.
To sample the architecture without installing anything, try out ANGEL, a JavaScript ISA simulator that boots an interactive session of riscv-linux on a simulated RISC-V machine in your browser.
RISC-V（發(fā)音為“Risk Five”）是一個開放的句喷、自由的ISA志珍，通過開放的標準協(xié)作實現(xiàn)了處理器創(chuàng)新的新時代斟薇。RISC-V ISA誕生于學術界和研究界，為未來50年的計算設計和創(chuàng)新鋪平了道路腹缩。
最終的用戶級ISA規(guī)范、一份壓縮的ISA規(guī)范草案阻课、一份特權(quán)ISA規(guī)范草案和一套RISC-V軟件工具宪郊，包括GNU/GCC軟件工具鏈、GNU/GDB調(diào)試器蹭越、LLVM編譯器障本、SPICK ISA模擬器、QEMU和驗證套件，現(xiàn)在可以下載驾霜。
要在不安裝任何東西的情況下對體系結(jié)構(gòu)進行采樣案训，可以嘗試Angel，一個JavaScript模擬器粪糙，它可以在瀏覽器中的一臺模擬RISC-V機器上啟動RISCVlinux的交互式會話强霎。
You can also visit the UC Berkeley Architecture Research projects page to see a number of RISC-V based projects including a high-performance, energy-efficient Rocket processor (a 64-bit RISC-V single-issue in-order core), suitable for both high-speed simulation and full synthesis, is available for download.
Our intent is to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference software simulators, cycle-accurate FPGA emulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites, and teaching materials.
您還可以訪問加州大學伯克利分校建筑研究項目頁面，查看一些基于RISC-V的項目蓉冈，包括高性能城舞、節(jié)能的火箭處理器（64位RISC-V單問題訂單核心），適用于高速模擬和全合成寞酿，可供下載家夺。
我們的目的是提供具有重要基礎設施支持的長壽命開放式ISA，包括文檔伐弹、編譯器工具鏈拉馋、操作系統(tǒng)端口、參考軟件模擬器惨好、周期精確的FPGA模擬器煌茴、高性能FPGA計算機、各種目標平臺設計的高效ASIC實現(xiàn)昧狮、可配置處理器generATORS景馁、架構(gòu)測試套件和教學材料
Key Features of the RISC-V ISA:
* Delivers a new level of software and hardware freedom on architecture in an open extensible way.
* Open ISA delivers easier support from a broad range of operating systems, software vendors and tool developers.
* The open source of hardware, RISC-V does not rely on a single supplier – offers multiple suppliers, therefore, supports unlimited potential for future growth.
* No other ISA is architected like the RISC-V ISA, allowing for user extensibility of the architecture without breaking existing extensions or incurring software fragmentation
RISC-V ISA的主要特點：
以開放的可擴展方式在體系結(jié)構(gòu)上提供新的軟件和硬件自由度。
開放式ISA提供了廣泛操作系統(tǒng)逗鸣、軟件供應商和工具開發(fā)人員的更簡單支持。
硬件的開放源代碼RISC-V不依賴于單個供應商绰精，它提供多個供應商撒璧，因此支持未來無限增長的潛力。
沒有任何其他的ISA像RISC-V ISA那樣架構(gòu)化笨使，允許用戶在不破壞現(xiàn)有擴展或?qū)е萝浖槠那闆r下擴展該架構(gòu)卿樱。
點擊左側(cè)的User-Level ISA Specification 進入新界面
? ? Please note, RISC-V ISA and related specifications are developed, ratified and maintained by RISC-V Foundation contributing members within the RISC-V Foundation Technical Committee. Operating details of the Technical Committee can be found in the RISC-V Foundation Workspace. Work on the specification is performed on GitHub and the GitHub issue mechanism can be used to provide input into the specification.
? ? The specifications shown below reflect the last official release. The most current version of the draft specification, which is in development within the Technical Committee, can be found here on GitHub.
請注意，RISC-V ISA和相關規(guī)范是由RISC-V基金會成員在RISC-V基金會技術委員會內(nèi)制定硫椰、批準和維護的繁调。技術委員會的操作細節(jié)可以在RISC-V基金會工作區(qū)找到。關于規(guī)范的工作是在GitHub上執(zhí)行的靶草，并且可以使用GitHub發(fā)布機制向規(guī)范提供輸入蹄胰。
下面顯示的規(guī)范反映了上一次正式發(fā)布。技術委員會正在開發(fā)的最新版本的規(guī)范草案可以在Github上找到奕翔。
