在FPGA設(shè)計(jì)中膝昆，可以從以下五個(gè)方面來改善設(shè)計(jì)的時(shí)序表現(xiàn)
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增加寄存器層級(jí)
增加寄存器層級(jí)娃弓，即在關(guān)鍵路徑上，通過插入中間寄存器的方法來對(duì)關(guān)鍵路徑進(jìn)行切割廓潜。該方法適用于對(duì)延時(shí)不敏感的設(shè)計(jì)中。
module fir( output [7:0] Y, input [7:0] A, B, C, X, input clk, input validsample); reg [7:0] X1, X2, Y; always @(posedge clk) if(validsample) begin X1 <= X; X2 <= X1; Y <= A* X+B* X1+C* X2; end endmodule優(yōu)化后：
module fir( output [7:0] Y, input [7:0] A, B, C, X, input clk, input validsample); reg [7:0] X1, X2, Y; reg [7:0] prod1, prod2, prod3; always @ (posedge clk) begin if(validsample) begin X1 <= X; X2 <= X1; prod1 <= A * X; prod2 <= B * X1; prod3 <= C * X2; end Y <= prod1 + prod2 + prod3; end endmodule對(duì)應(yīng)RTL為：
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結(jié)構(gòu)并行化
結(jié)構(gòu)并行化策略指的是，通過將關(guān)鍵路徑上的較大的邏輯結(jié)構(gòu)進(jìn)行重組辩蛋，使用較小的并行結(jié)構(gòu)進(jìn)行實(shí)現(xiàn)呻畸。這種方法適用于一些滿足條件（可并行實(shí)現(xiàn)）的串行結(jié)構(gòu)。
X = {A, B} X * X = {A, B} * {A, B} = {(A * A), (2 * A * B), (B * B)};可優(yōu)化為：
module power3( output [7:0] XPower, input [7:0] X, input clk); reg [7:0] XPower1; // partial product registers reg [3:0] XPower2_ppAA, XPower2_ppAB, XPower2_ppBB; reg [3:0] XPower3_ppAA, XPower3_ppAB, XPower3_ppBB; reg [7:0] X1, X2; wire [7:0] XPower2; // nibbles for partial products (A is MS nibble, B is LS nibble) wire [3:0] XPower1_A = XPower1[7:4]; wire [3:0] XPower1_B = XPower1[3:0]; wire [3:0] X1_A = X1[7:4]; wire [3:0] X1_B = X1[3:0]; wire [3:0] XPower2_A = XPower2[7:4]; wire [3:0] XPower2_B = XPower2[3:0]; wire [3:0] X2_A = X2[7:4]; wire [3:0] X2_B = X2[3:0]; // assemble partial products assign XPower2 = (XPower2_ppAA << 8)+(2*XPower2_ppAB << 4)+XPower2_ppBB; assign XPower = (XPower3_ppAA << 8)+(2*XPower3_ppAB << 4)+XPower3_ppBB; always @(posedge clk) begin // Pipeline stage 1 X1 <= X; XPower1 <= X; // Pipeline stage 2 X2 <= X1; // create partial products XPower2_ppAA <= XPower1_A * X1_A; XPower2_ppAB <= XPower1_A * X1_B; XPower2_ppBB <= XPower1_B * X1_B; // Pipeline stage 3 // create partial products XPower3_ppAA <= XPower2_A * X2_A; XPower3_ppAB <= XPower2_A * X2_B; XPower3_ppBB <= XPower2_B * X2_B; end endmodule對(duì)應(yīng)RLT圖為
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邏輯結(jié)構(gòu)平行化
所謂了邏輯結(jié)構(gòu)平行化悼院，即取消一下不必要的優(yōu)先級(jí)鏈級(jí)結(jié)構(gòu)擂错，這跟第2點(diǎn)有點(diǎn)類似。通俗的講樱蛤，多用case钮呀，少用if else。
module regwrite( output reg [3:0] rout, input clk, in, input [3:0] ctrl); always @(posedge clk) if(ctrl[0]) rout[0] <= in; else if(ctrl[1]) rout[1] <= in; else if(ctrl[2]) rout[2] <= in; else if(ctrl[3]) rout[3] <= in; endmodule可優(yōu)化為：
module regwrite( output reg [3:0] rout, input clk, in, input [3:0] ctrl); always @(posedge clk) begin if(ctrl[0]) rout[0] <= in; if(ctrl[1]) rout[1] <= in; if(ctrl[2]) rout[2] <= in; if(ctrl[3]) rout[3] <= in; end endmodule對(duì)應(yīng)RTL為：
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與
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寄存器平衡
寄存器平衡昨凡，就是將關(guān)鍵路徑上各個(gè)寄存器之間的邏輯重新進(jìn)行劃分爽醋，從而使得每級(jí)寄存器之間的邏輯延時(shí)達(dá)到均衡。
module adder( output reg [7:0] Sum, input [7:0] A, B, C, input clk); reg [7:0] rA, rB, rC; always @(posedge clk) begin rA <= A; rB <= B; rC <= C; Sum <= rA + rB + rC; end endmodule優(yōu)化后
module adder( output reg [7:0] Sum, input [7:0] A, B, C, input clk); reg [7:0] rABSum, rC; always @(posedge clk) begin rABSum <= A + B; rC <= C; Sum <= rABSum + rC; end endmodule對(duì)應(yīng)RLT圖為：
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與
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路徑重配置
路徑重配置策略便脊，即將關(guān)鍵邏輯上的一些邏輯運(yùn)算轉(zhuǎn)移到相鄰的路徑上去蚂四。
module randomlogic( output reg [7:0] Out, input [7:0] A, B, C, input clk, input Cond1, Cond2); always @(posedge clk) if(Cond1) Out <= A; else if(Cond2 && (C < 8)) Out <= B; else Out <= C; endmodule可優(yōu)化為：
module randomlogic( output reg [7:0] Out, input [7:0] A, B, C, input clk, input Cond1, Cond2); wire CondB = (Cond2 & !Cond1); always @(posedge clk) if(CondB && (C < 8)) Out <= B; else if(Cond1) Out <= A; else Out <= C; endmodule對(duì)應(yīng)RTL圖為
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和
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