1填抬、用VPN下載器件庫(kù)
版本和IDE一樣
http://fpgasoftware.intel.com/?edition=standard
2飒责、用管理員權(quán)限打開quartus ，Tools >Install Devices選擇器件庫(kù)
3宏蛉、新建項(xiàng)目
選和板子一樣的設(shè)備
4拾并、寫代碼編譯
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY Test1 is
PORT(
clk:in STD_LOGIC;
led1:out STD_LOGIC_VECTOR(11 DOWNTO 0));
END Test1;
ARCHITECTURE light OF Test1 IS
SIGNAL clk1 :std_logic;
BEGIN
P1:PROCESS (clk)
VARIABLE count:INTEGER RANGE 0 TO 9999999;
BEGIN
IF clk'EVENT AND clk='1' THEN
IF count<=4999999 THEN
clk1<='0';
count:=count+1;
ELSIF count>=4999999 AND count<=9999999 THEN
clk1<='1';
count:=count+1;
ELSE count:=0;
END IF;
END IF;
END PROCESS ;
P2:PROCESS(clk1)
variable count1:INTEGER RANGE 0 TO 16;
BEGIN
IF clk1'event AND clk1='1'THEN
if count1<=13 then
if count1=12 then
count1:=0;
end if;
CASE count1 IS
WHEN 0=>led1<="111111111110";
WHEN 1=>led1<="111111111101";
WHEN 2=>led1<="111111111011";
WHEN 3=>led1<="111111110111";
WHEN 4=>led1<="111111101111";
WHEN 5=>led1<="111111011111";
WHEN 6=>led1<="111110111111";
WHEN 7=>led1<="111101111111";
WHEN 8=>led1<="111011111111";
WHEN 9=>led1<="110111111111";
WHEN 10=>led1<="101111111111";
WHEN 11=>led1<="011111111111";
WHEN OTHERS=>led1<="111111111111";
END CASE;
count1:=count1+1;
end if;
end if;
end process;
END light;
5个榕、設(shè)置管腳
6芥喇、下載程序
把Unused Pins中的Reverse all unused pins:選擇為As input tri-stated凰萨。意思是說(shuō)把不用的管腳設(shè)置為輸入三態(tài)械馆，Quartus默認(rèn)這個(gè)選項(xiàng)是不用的管腳輸出接地武通，這樣最典型的現(xiàn)象是很可能你一下載代碼到板子上蜂鳴器就響個(gè)不停
因?yàn)檫M(jìn)程是并行的，所以不能在兩個(gè)進(jìn)程中給同一個(gè)變量賦值尾菇。
一個(gè)process里面只能有一個(gè)上升沿檢測(cè)語(yǔ)句
