-
Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.
構(gòu)建一個從 0 到 15（含）計數(shù)的 4 位二進制計數(shù)器逸爵，周期為 16找筝。復(fù)位輸入是同步的静尼，應(yīng)將計數(shù)器復(fù)位為 0。
image.png
module top_module (
input clk,
input reset, // Synchronous active-high reset 同步高電平有效
output [3:0] q);
always @(posedge clk)
if (reset)
q <= 4'd0;
else
q <= q + 4'd1;
endmodule
---------------------------官網(wǎng)答案-------------------------------
module top_module(
input clk,
input reset,
output reg [3:0] q);
always @(posedge clk)
if (reset)
q <= 0;
else
q <= q+1; // Because q is 4 bits, it rolls over from 15 -> 0.
// If you want a counter that counts a range different from 0 to (2^n)-1,
// then you need to add another rule to reset q to 0 when roll-over should occur.
endmodule
- Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.
構(gòu)建一個從 0 到 9（含）計數(shù)的十進制計數(shù)器式散，周期為 10。復(fù)位輸入是同步的尸昧，應(yīng)將計數(shù)器復(fù)位為 0腹忽。
我的思路是想著把10，11没隘，12懂扼，13，14右蒲，15的輸入信號為不是所需信號阀湿，都將其置為0
但是結(jié)合官網(wǎng)所給的參考答案，好像自己的解題思路好像還是不太對瑰妄，因為這是計數(shù)器陷嘴，將9置為0之后就重新開始了，根本沒辦法有10產(chǎn)生啊间坐。哎灾挨！
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q);
reg[3:0] i;
always@(posedge clk)
if(reset)
q <= 0;
else if(q > 4'd8 )
q <= 0;
else
q <= q + 1 ;
endmodule
-------------------------官網(wǎng)解答-------------------------------------------
module top_module(
input clk,
input reset,
output reg [3:0] q);
always @(posedge clk)
if (reset || q == 9) // Count to 10 requires rolling over 9->0 instead of the more natural 15->0
q <= 0;
else
q <= q+1;
endmodule
- Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1.
制作一個從 1 到 10 的十位計數(shù)器，包括 1 到 10竹宋。復(fù)位輸入是同步的劳澄，應(yīng)將計數(shù)器復(fù)位為 1。
module top_module (
input clk,
input reset,
output [3:0] q);
always@(posedge clk)
if(reset || q == 4'd10)
q <= 4'd1;
else
q <= q + 1;
endmodule
-------------------------------官網(wǎng)答案------------------------------------
無
-
Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.
構(gòu)建一個從 0 到 9 計數(shù)的十進制計數(shù)器逝撬，周期為 10浴骂。復(fù)位輸入是同步的，應(yīng)該將計數(shù)器復(fù)位為 0宪潮。我們希望能夠暫停計數(shù)器溯警，而不是總是在每個時鐘周期遞增，所以slowena輸入指示計數(shù)器何時應(yīng)該增加狡相。
image.png
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q);
always@(posedge clk)
if(reset)
q <= 4'd0;
else if(slowena) begin
if(q == 9)
q <= 4'd0;
else
q <= q + 1;
end
endmodule
這里需要知道引入了slowena的輸入信號梯轻，只有當(dāng)這個信號有效時計數(shù)器才會執(zhí)行計數(shù)增加的功能，這也就是為什么要將q==9的代碼寫在if(slowena)代碼塊中尽棕，就是這個原因了
Design a 1-12 counter with the following inputs and outputs:
ResetSynchronous active-high reset that forces the counter to 1EnableSet high for the counter to runClkPositive edge-triggered clock inputQ[3:0]The output of the counterc_enable,c_load,c_d[3:0]Control signals going to the provided 4-bit counter, so correct operation can be verified.
You have the following components available:the 4-bit binary counter (
count4) below, which has Enable and synchronous parallel-load inputs (load has higher priority than enable). Thecount4module is provided to you. Instantiate it in your circuit.logic gates
module count4(
input clk,
input enable,
input load,
input [3:0] d,
output reg [3:0] Q
);
The c_enable, c_load, and c_d outputs are the signals that go to the internal counter's enable, load, and d inputs, respectively. Their purpose is to allow these signals to be checked for correctness.
設(shè)計一個具有以下輸入和輸出的 1-12 計數(shù)器：
復(fù)位同步高電平有效復(fù)位喳挑，強制計數(shù)器為 1
啟用設(shè)置高以使計數(shù)器運行
Clk正邊沿觸發(fā)時鐘輸入
Q[3:0]計數(shù)器的輸出
c_enable, c_load, c_d[3:0]控制信號進入提供的 4 位計數(shù)器，因此可以驗證正確的操作滔悉。
您有以下可用組件：
下面的 4 位二進制計數(shù)器 ( count4 )伊诵，它具有啟用和同步并行加載輸入（加載的優(yōu)先級高于啟用）。count4模塊提供給您回官。在你的電路中實例化它曹宴。
邏輯門如上
c_enable 、c_load和c_d輸出是分別進入內(nèi)部計數(shù)器的enable歉提、load和d輸入的信號笛坦。它們的目的是允許檢查這些信號的正確性区转。
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
assign c_enable = enable; // 提供使能
assign c_load = reset | ((Q == 4'd12) & enable) ; // 對count 4進行復(fù)位操作
assign c_d = 1'h1; // 給與復(fù)位初始值
count4 the_couter(.clk(clk),.enable(c_enable),.load(c_load),.Q(Q),.d(c_d));
endmodule
- From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).
從 1000 Hz 時鐘導(dǎo)出一個稱為OneHertz的 1 Hz 信號，該信號可用于驅(qū)動一組小時/分鐘/秒計數(shù)器的啟用信號以創(chuàng)建數(shù)字掛鐘版扩。由于我們希望時鐘每秒計數(shù)一次废离，因此OneHertz信號必須每秒準(zhǔn)確地斷言一個周期。使用模 10 (BCD) 計數(shù)器和盡可能少的其他門構(gòu)建分頻器礁芦。還要從您使用的每個 BCD 計數(shù)器輸出使能信號（c_enable[0] 為最快的計數(shù)器蜻韭，c_enable[2] 為最慢的）。
好吧宴偿，這一題說實話湘捎，屬實為難我了。真心沒看懂窄刘！
參考Troke博主的解題思路：
題目分析：題目希望我們用1000hz的時鐘來輸出一個1hz的信號（即1000的分頻器），同時將輸出使能信號也進行輸出舷胜，這實際上還是一個計數(shù)的問題娩践。題目中給了我們一個模10的bcd計數(shù)器，(即計數(shù)從0到9計數(shù))我們可以通過例化這個模塊來實現(xiàn)輸出1hz信號烹骨，具體思路就是將1000按位進行分解翻伺，由于是從000開始，所以只需要計數(shù)到999時沮焕，輸出就能達成目標(biāo)吨岭。所以可以將1000分解成個位、十位峦树、百位辣辫、千位，然后每個位按一定條件進行0-9的循環(huán)計數(shù)魁巩，下面用時序圖來描述下整個大概的流程
————————————————
版權(quán)聲明：本文為CSDN博主「Troke」的原創(chuàng)文章急灭，遵循CC 4.0 BY-SA版權(quán)協(xié)議，轉(zhuǎn)載請附上原文出處鏈接及本聲明谷遂。
原文鏈接：https://blog.csdn.net/weixin_45931009/article/details/118912900
/*我的解答*/
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
);
wire [3:0] Q0,Q1,Q2; //定義個位葬馋，十位，百位上的數(shù)
bcdcount counter0 (clk, reset, c_enable[0],Q0); //個位
bcdcount counter1 (clk, reset, c_enable[1],Q1); //十位
bcdcount counter2 (clk, reset, c_enable[2],Q2); //百位
//使用組合邏輯
always @(*) begin
if(reset == 1'b1)
c_enable <= 3'b001; //先讓個位上的數(shù)進行0-9的計數(shù)
else begin
if(Q0 == 4'd9) begin //當(dāng)個位上的數(shù)計數(shù)到9時
c_enable <= 3'b011; //讓十位上也開始計數(shù)
if(Q1 == 4'd9) begin //當(dāng)十位上的數(shù)也計數(shù)到9時
c_enable <= 3'b111; //讓百位上也開始計數(shù)
end
end
else
c_enable <= 3'b001;
end
end
always @(*) begin
if(reset == 1'b1)
OneHertz = 1'b0;
else if(Q0 == 4'd9 && Q1 == 4'd9 && Q2 == 4'd9) //滿足三個位上都為9時肾扰，直接輸出
OneHertz = 1'b1;
else
OneHertz = 1'b0;
end
endmodule
